1. Field of the Invention
The present invention relates to a semiconductor device having gate electrodes, and a method of manufacturing the same.
2. Description of Related Art
General LSIs using FETs are designed in various ways, by using arbitrary values to a gate-to-gate spacing within the scope of design rules.
However, with progress of shrinkage of elements, it has been known that difference in the gate spacing might affect gate length, impurity distribution, carrier mobility and so forth, and might systematically vary transistor characteristics (see P. Grudowski et al., “1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations”, Symp. on VLSI Tech., p. 76 (2006) (Non-Patent Document 1) and H. Tsuno et al., “Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation” Symp. on VLSI Tech., p. 204 (2007) (Non-Patent Document 2).
Transistors having diffusion layers at the ends of the active region may make the gate spacing closer to a constant value, by forming a dummy gate on the element isolation region.
However, for transistors having no diffusion layers at the ends of the active region, it is difficult to provide the dummy gate without careful consideration, from the viewpoint of element isolation,
On the other hand, adding constraints to the design of gate spacing may limit the degree of freedom of design, which leads to reduce the competitiveness.
A semiconductor device having, as shown in FIG. 9, dummy gates 116 on both ends of a transistor 103, which has a shape to straddle a diffusion layer 122 and an element isolation region 113, has been proposed (see Japanese Unexamined Patent Application Publication No. H8-236767 (Patent Document 1), for example).
It has been reported that, by forming the dummy gates 116 which straddles the diffusion layers 122 and the element isolation regions 113 in this way, variation in the gate length ascribable to gate spacing can be reduced, so that variation in the transistor characteristics may be suppressed.
This configuration is, however, applicable only to transistors having the diffusion layers at the ends of the active region, and is not readily applicable to target transistor having additional transistor(s) formed on one side, or on both sides thereof.
A semiconductor device having, as shown in FIG. 10, dummy gates 216, 217 on the diffusion layers 222 on both ends of a transistor 203, or on the element isolation region 213 has been proposed (see Japanese Unexamined Patent Application Publication No. 2002-190589 (Patent Document 2), for example).
It has been reported that, by forming the dummy gates 216, 217 on the diffusion layers 222 on both ends of a transistor 203, or on the element isolation region 213 in this way, variation in the sidewall width ascribable to gate spacing can be reduced, so that the variation in the transistor characteristics can be suppressed.
In the exemplary case of Patent Document 2, the configuration is also employed to the transistor having no diffusion layers formed at the ends of the active region. Formation of the dummy gates in the active region may, however, make the diffusion layer divided into regions on the left sides and the right sides of the dummy gates, so that, in a practical MOS transistor circuit, the dummy gates may be formed only to limited transistors, similarly to the transistor described in the Patent Document 1.
A semiconductor device having, as shown in FIG. 11, dummy gates 316 on the element isolation regions 313 in the vicinity of transistors 303, and a semiconductor device having, as shown in FIG. 14, dummy patterns 317 on the element isolation regions 313 in the vicinity of the transistors 303 have been proposed [see Japanese Unexamined Patent Application Publication No. 2004-289138 (Patent Document 3), for example].
It has been reported that, by forming the dummy gates 316 or the dummy patterns 317 in this way, thickness of a silicide layer 325 on the diffusion layer 322 can be made uniform, so that the variation in the transistor characteristics can be suppressed.
The configuration of forming the dummy gates on the element isolation regions is, however, all the same with that described in the Patent Document 2, and is applicable again only to a limited transistors. Although the configuration is different from that of the Patent Document 2 in that not only the dummy gates but also the dummy patterns are used, the dummy gates or the dummy patterns are formed still on the element isolation region, so that a problem remains in that the configuration is applicable only to a limited transistors which reside at the ends of the active region.